hdl - verilog, why is this illegal reference to net -

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i new verilog don't why illegal reference net signal (subcounter_of_counter). mean it's combinational logic

thanks in advance :)

wire [n-1:0] subcounter_of_counter; reg [n-1:0] mask,free;      @(*) begin //command or id or mask or free or subcounter_of_counter         if (command==increment) begin             (int = 0; < n; i=i+1)begin                 if (i<id) begin                     subcounter_of_counter[i]=1'b0;                 end else if (i==id) begin                     subcounter_of_counter[i]=1'b1;                 end else begin                     if( (|mask[id+1:i]) || (|free[id+1:i]) ) begin                         subcounter_of_counter[i]=1'b0;                     end else begin                         subcounter_of_counter[i]=1'b1;                     end                 end             end         end         end

a wire nettype, , nettype cannot assigned in always blocks or initial blocks.
change subcounter_of_counter wire reg resolve issue. reg keyword logic type , not explicitly mean synthesize register.


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