verilog multiplication results is zero? -

i'm trying multiply 2 32 bit signed fractional number (1 sign bit, 8 integer bit, 23 fraction bit)

the first 1 is

32'b0_00000001_00000000000000000000000 // 1.00

the 2nd 1 is

32'b0_00000100_00000000000000000000000 // 4.00

when example

output signed[31:0] a;

assign = 32'b0_00000001_00000000000000000000000 * 32'b0_00000100_00000000000000000000000;

the results zero? why isn't 4?

kindly please me in part mistaken , should do. thank much

regards

isaac

because trying assign 64 bit value 32 bit wire, , verilog truncate value, keeping lower 32 bits of result, zero.

to have proper result, can this:

module mult;   reg [31:0] = 32'b0_00000001_00000000000000000000000;  // 1.0   reg [31:0] b = 32'b0_00000100_00000000000000000000000;  // 4.0    reg [63:0] t;   reg [31:0] c;    initial begin     t = * b;     c = t[54:23];      $display ("%b",c);     $finish;   end   endmodule