constraints - BASYS3 Lighting the leds -
i'm beginner fpga programming , working on basys3
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in system-verilog code have 2 2 bit outputs: la , lb. assuming these 2 traffic lights , 00 means red, 10 means yellow, 11 means green. if output red, 3 leds light. don't know how implement in constraint file. normally, when output 1, want led light , write kind of code:
set_property package_pin u14 [get_ports {la[0]}] set_property iostandard lvcmos33 [get_ports {la[0]}]
but time want led light when output 0. maybe can write 2 more outputs become opposite of real outputs , can use them in constraint wonder can directly implement want in constraint file?
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